Method of neutralizing local defects in charge couple device structures

ABSTRACT

A process and structure are disclosed whereby dopants are used to surround crystalline defects in a semiconductor crystal thereby creating a PN junction which isolates the defect site from the remaining semiconductor substrate and preventing charge flow through the defect into the potential well of a charge coupled device structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to a process and structure for neutralizingcrystalline defects in a charged coupled device structure, inparticular, for isolating the defect from the remaining substrate with aPN junction.

2. Description of the Prior Art

The operation of a charged coupled device, commonly referred to as CCD,basically consists of storing electric charge at the surface of asemiconductor in which a potential well has been created, and movingthis charge across the surface of the semiconductor by applyingsequentially increasing electric potentials across the semiconductorsurface.

By employing a series of metal gates insulated from a silicon substrateby a layer of silicon dioxide, a depletion region is formed under eachof the metal gates by applying the appropriate voltage to theappropriate gate electrode. The potential well created by the depletionregion under the gate electrode attracts a charge flow into thepotential well, and acts as a storage well for the charge packet. Byapplying a series of sequentially increasing electric pulses to the gateelectrodes, the charge packet may be transported into each successiveneighboring potential well. The charge packet is thereby progressivelytransported along an array of gate regions by the sequential applicationof the appropriate electric pulses.

Although the immediate application of a charge coupled device is todigital electronics, its application may be expanded to analog delaylines whereby the various amounts of charge stored in the potential wellare given numeric significance. When the amount of charge stored in thepotential well is given numeric significance, crystalline defects in thesemiconductor substrate have serious adverse effects on deviceoperation. Defects in the semiconductor substrate, which tend toaggregate near the surface of the semiconductor, interact with thepotential well so as to introduce additional charge flow into thepotential well. This defect is a region of the semiconductor where thesingle crystal structure is not maintained and generation-recombinationrates are greater than elsewhere in the material. When the defectintersects the potential well, the increased generation-recombinationrate causes a flow of carriers into the potential well. This additionalcharge flow into the potential well increases the amount of chargestored in the charge packet, thereby undesirably altering the analogcharacteristics of the charge packet. The details of the mechanism bywhich such additional charge flows into the potential well has receivedextensive treatment in technical literature. For purposes of simplicity,such mechanisms will not be discussed here.

Neutralizing the effect of the crystalline defect and thereby preventingadditional charge flow into the potential well would improve theoperating characteristics of the charge coupled device and improve itsreliability as an analog delay line.

SUMMARY OF THE INVENTION

The object of the present invention is to neutralize crystalline defectsin a semiconductor substrate which enhance additional charge flow intothe potential well created by a voltage applied across an insulated gatestructure which forms a part of the charge coupled device.

In accordance with the present invention, a process is disclosed forisolating one or more defects in a semiconductor substrate byselectively forming a PN junction between the defect and the remainderof the substrate. In the preferred embodiment, this is performed bydiffusing a dopant of second conductivity type into the semiconductorsubstrate of a first conductivity type, thereby forming a firstdiffusion region of nearly uniform depth and a second diffussion regionbetween the defect and the remainder of the substrate. The firstdiffusion region is removed, leaving the second diffusion region to forma PN junction which isolates the defect site from the remainder of thesubstrate.

Additionally, a charge coupled device with defect sites isolated inaccordance with the above described process is disclosed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified schematic illustration of a cross-section of acharge coupled device with defect sites as constructed using prior artprocessing;

FIG. 2 is a flow chart summarizing the process steps for neutralizingdefect sites in the semiconductor substrate;

FIGS. 3, 4 and 5 are vertical cross-sectional views schematicallyillustrating structures resulting from the disclosed process; and

FIG. 6 is a schematic illustration of a charge coupled device withdefect sites isolated from the remaining semiconductor substrate by a PNjunction.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a simplified schematic vertical cross-sectional view of acharge coupled device as constructed using prior art processing withcrystal defects in the semiconductor substrate. The semiconductorsubstrate 20 is typically silicon, and may be lightly doped with N-typeimpurities. An insulating layer 22, typically silicon dioxide, issandwiched between the semiconductor substrate 20 and metal gates 24,26, 28, 30 and 34. An input gate 30 is adjacent to a source 32 forsupplying positive charges consisting of a diffused bed of P-material. Asimilar output gate 34 is located at the opposite end of the chargecoupled device adjacent to a collector 36 for positive charge consistingof a diffused bed of P-material. By applying the appropriate voltage toinput gate 30, a potential well 40 is created under the input gate 30into which positive charges 41 flow. The sequential application ofincreasing voltage to neighboring gate electrodes 24, 26, 28 and 34 willresult in the sequential creation of potential wells 44, 46, 48 and 50into which the charge packet 41 will preferentially flow. Typical defectsites 60 intersecting or contained within the potential wells 40, 44,46, 48 and 50 introduce additional charge flow into the potential wells40, 44, 46, 48 and 50, thereby distorting the charge level within thepotential well, and altering the output signal.

FIG. 1 is a simplified charge coupled device illustrating theinteraction of defects with the potential wells. In practical devices, amore complicated gate structure may be required. Although only fivegates have been shown in FIGS. 1 and 6, additional gates or fewer gatesmay be used. The gate structure has been simplified because a morecomplex structure is not required to illustrate this interaction.

FIG. 2 is a flow chart summarizing the process steps which neutralizethe effect of a typical defect site 60. A layer of dopant ofconductivity type opposite from the conductivity type of thesemiconductor substrate is diffused into the semiconductor substrate. AP-doped layer may be formed by depositing a heavily doped glass layer onthe surface of an N-type substrate followed by heating the substrate tocause the P-type dopants to diffuse into the substrate. This is awell-known prior art process. Alternatively, ion implantation may beused to implant a shallow layer of P-material in the N-substratefollowed by heating the substrate to cause the P-type dopants to diffuseinto the substrate. The effect of the diffusion is to create twodiffusion regions. The first region is of nearly uniform depth, and thesecond region located at the defect sites is of slightly greater depthbecause of the higher diffusion constant at the defect site. If a P-typelayer is used, the defect will be surrounded by P-material. Diffusiondepths are typically less than 1μm.

The second step in the process is to remove the first diffusion layer,thereby leaving the second diffusion region in the semiconductorsubstrate. This second diffusion region forms a PN junction with theremaining substrate, thereby isolating the defect. The removal isaccomplished by processes known in the art such as chemical etching oranodic oxidation.

FIGS. 3, 4 and 5 schematically illustrate vertical cross-sectional viewsof the semiconductor substrate as the processing steps illustrated inFIG. 2 are performed. A semiconductor substrate 100 lightly doped withN-type impurities with defect sites 110 is processed so as to form aP-type layer 120 on the semiconductor substrate 100. Layer 120 may beformed by ion implanting a shallow layer of P-material in thesemiconductor substrate 100 using known techniques. A suitable P-typematerial is boron. Alternatively, the process utilizing a P-doped glasslayer previously described may be used to form layer 120. Those skilledin the art will appreciate that other techniques and other P-typematerials may be used.

The structure illustrated in FIG. 3 is heated, causing the P-dopants todiffuse further into the substrate 100. This results in two diffusionregions 130 and 132 as illustrated in FIG. 4. The first diffusion region130 is of nearly uniform depth, and the second diffusion region 132 isof slightly greater depth. The second diffusion region 132 resultsbecause of a higher diffusion constant near the defect sites 110.

The first diffusion layer 130 is then removed by techniques known in theprior art, such as chemical etching or anodic oxidation. The resultingstructure is schematically illustrated in FIG. 5. The defect sites 110located in semiconductor substrate 100 isolated from the remainingsemiconductor substrate 100 by PN junction 150. The charge coupleddevice is constructed on semiconductor substrate 100 using conventionaltechniques.

The effect of the second diffusion region 132 forming a P-well aroundthe defect site 110 is to form a PN junction near the defect. The Fermilevel band diagrams of the PN junction without bias as it intersects apotential well in a CCD structure are such that the PN junction forms abarrier which inhibits the flow of charge into the potential well,thereby neutralizing the defects.

Although these process steps illustrated and discussed are for isolatingdefects in an N-type semiconductor substrate, those skilled in the artwill appreciate that similar steps for a P-type semiconductor substratemay be performed by using an N-doped diffusion layer to surround thedefect. Such processing steps would result in isolating the defect by aPN junction.

FIG. 6 is a schematic cross-sectional illustration of a typical chargecoupled device with PN junctions isolating the defect from the remainderof the substrate. The device is constructed on an N-type semiconductorsubstrate 200 with a source of positive charges 210 and a collector forpositive charges 212 consisting of two diffused beds of P-material.Metal gates 220, 224, 226, 228, 230 are insulated from the semiconductorsubstrate 200 by insulating layer 250 which is typically silicondioxide. Charge packet 252 contained by potential well 254 flows intopotential well 256. Typical defect sites 260 are isolated from theremaining semiconductor substrate by PN junction 262, therebyneutralizing their effect on the potential wells 254 and 256.

FIG. 6 is intended to indicate a CCD structure in which the defect siteshave been neutralized. In a practical device, a more complicated gatestructure may be required to assure efficient transfer of the chargepacket to each succeeding potential well.

I claim:
 1. A method of preventing charge leakages in potential wells ofa charge coupled device which are caused by defects located in asemiconductor substrate in which the potential wells are formed andwhich defects may intersect the potential wells, the methodcomprising:diffusing a dopant of a second conductivity into asemiconductor substrate having a continuous surface to provide a firstdiffused region of approximately uniform depth and second deeperdiffused regions surrounding any defect in said substrate; and removingonly said first diffused region from said substrate, said substratehaving said second diffused regions surrounding any defects in order toneutralize the effect of any of said defects in the substrate in whichthe potential wells are to be formed.
 2. A method in accordance withclaim 1 wherein said doped material of second conductivity is ofopposite conductivity type than said semiconductor substrate of firstconductivity.
 3. A method in accordance with claim 1 further includingion implanting dopants of a second conductivity type in said substrateprior to diffusing said dopants into said substrate.
 4. A method inaccordance with claim 1 wherein said step of removing said firstdiffused region is achieved by chemical etching.
 5. A method inaccordance with claim 1 wherein said step of removing said firstdiffused region is achieved by anodic oxidation.
 6. A method inaccordance with claim 1 wherein said dopant is boron.